Apparatus and method for decoding compressed digital video data
US6282244A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1996 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Aug 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for decoding compressed digital video data which has been compressed, for example in a format compliant with the Motion Picture Experts Group I (MPEG) standard or the Joint Picture Experts Group (JPEG) standard. The apparatus and method allows a fast decoding rate for the compressed digital video data. A variable length decoding (VLD) circuit is used to generate a first bit sequence of a fixed length by decoding the received compressed digital video data. Then, an inverse quantizer is used to convert the first bit sequence by inverse quantization into a second bit sequence. A zig-zag buffer is then used to store the second bit sequence at specific locations and output a plurality of frequency-division binary signal bits concurrently in parallel. An inverse discrete cosine transfer (IDCT) circuit is used to process the plurality of frequency-division binary signal bits according to an inverse discrete cosine transfer function, to generate a plurality of time-division binary signal bits. These signal bits are combined into a time-division serial binary signal representative of decoded data for the compressed digital video data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.