Multi-port memory and a data processor accessing the same
US6282505A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Aug 14, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory of a super-scalar or VLIW processor to concurrently process a plurality of memory accesses, to provide a memory capable of multi-port access operation, there is provided a unit which subdivides the cache memory into a plurality of memory banks for concurrent operations thereof and which allocates memory ports independently to the respective memory banks. In a first cycle, the first and second memory ports are allocated to the first and second memory banks, respectively. If a hit occurs, the plural accesses are completed in one cycle. If a miss results, the first and second memory ports are allocated respectively to the second and first memory banks in a second cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.