High data density RISC processor
US6282633A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RISC processor implements an instruction set which, in addition to optimizing a relationship between the number of instructions required for execution of a program, clock period and average number of clocks per instruction, also is designed to optimize the equation S=IS * BI, where S is the size of program instructions in bits, IS is the static number of instructions required to represent the program (not the number required by an execution) and BI is the average number of bits per instruction. Compared to conventional RISC architectures, this processor lowers both BI and IS with minimal increases in clock period and average number of clocks per instruction. The processor provides good code density in a fixed-length high-performance encoding based on RISC principles, including a general register with load/store architecture. Further, the processor implements a simple variable-length encoding that maintains high performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.