Technique for sharing parity over multiple single-error correcting code words
US6282686A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. Each logical group uses a single error correcting code to detect and correct bit errors. A parity bit is appended to a data block that includes a plurality of logical groups. The parity bit may be used in conjunction with the single error correcting codes to determine whether a detected error is a single bit error or a multiple bit error. If the detected error is a single bit error, the error correction codes may be used to correct the error. If the detected error is a multiple bit error, an uncorrectable error may be reported.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.