Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure
US6284594A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | May 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for simultaneously forming a polysilicon gate structure, for a transfer gate transistor, and a polysilicon top plate, for a capacitor structure, on an underlying planar surface, has been developed. The process features the formation of a polysilicon bottom plate, for the capacitor structure, embedded in a first opening in composite insulator layer, and the formation of an active device region, for a transfer gate transistor structure, via the selective growth of an epitaxial silicon layer, in a second opening of the composite insulator layer, resulting in a planar top surface topography. The presence of this topography reduces the risk of residual polysilicon, present after patterning of the polysilicon gate structure, and of the capacitor, polysilicon top plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.