Integration scheme for multilevel metallization structures
US6284619A · kind A · utility
12Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Jun 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming multilevel metallization structures that improve semiconductor reliability. Multilevel metallization structures are formed through a two-step etch process which alleviates the problem of conductive etch residue forming between metal layers in multilevel structures. The resulting metallization structure has sidewall insulators on selected layers that prevent conductive etch residue from forming between the metal layers. The integration scheme of the present invention is especially applicable to metal-insulator-metal (MIM) capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.