Power transistor with silicided gate and contacts
US6284669A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1998 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Oct 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A power field effect transistor is disclosed that includes polysilicon gate bodies (40) and (42), which includes platinum silicide contact layers (74) and (78) disposed on the outer surfaces of bodies (40) and (42), respectively. In addition, the device comprises an n+drain region (64) which also has a platinum silicide drain contact layer (76) formed on its outer surface and platinum silicide source contact layers (75) and (77). During formation, sidewall spacers (50) and (52), as well as mask bodies (70) and (72) are used to ensure that platinum silicide layer (76) spaced apart from both gate bodies (40) and (42) and platinum silicide gate contact layers (74) and (78).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.