Digital clock recovery loop
US6285261A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Jul 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.