Memory cell
US6285619A · kind A · utility
6Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.