Queued arbitration mechanism for data processing system
US6286068A · kind A · utility
11Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.