Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
US6286090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1998 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | May 26, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique selectively imposes inter-reference ordering between memory reference operations issued by a processor of a multiprocessor system to addresses within a page pertaining to a page table entry (PTE) that is affected by a translation buffer (TB) miss flow routine. The TB miss flow is used to retrieve information contained in the PTE for mapping a virtual address to a physical address and, subsequently, to allow retrieval of data at the mapped physical address. The PTE that is retrieved in response to a memory reference (read) operation is not loaded into the TB until a commit-signal associated with that read operation is returned to the processor. Once the PTE and associated commit-signal are returned, the processor loads the PTE into the TB so that it can be used for a subsequent read operation directed to the data at the physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.