Method and system for optimizing the fetching of dispatch groups in a superscalar processor
US6286094A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Mar 5, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.