Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein
US6286126A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Apr 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus and computer program products are provided that perform the operations of extracting first estimates of the resistance and capacitance of each of a first plurality of nets in an integrated circuit and then determining, for each of the first plurality of nets, a respective maximum delay model that attributes all of the first estimate of the resistance of the respective net to a front-end of the net and all of the first estimate of the capacitance of the respective net to a back-end of the net. Respective minimum delay models are also obtained for each of the first plurality of nets. Each of these minimum delay models attributes all of the first estimate of the resistance of the respective net to the back-end of the net and all of the first estimate of the capacitance of the respective net to a front-end of the net. These minimum and maximum delay models are then used in the determination of minimum and maximum delay estimates for each of the first plurality of nets. The delay estimates are then used to determine a net timing error bound associated with each net. These net timing error bounds are then filtered against a user-specified net timing error tolerance to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.