Vivek Raghavan
7Patents
4h-index
12Co-inventors
54Inventor score
Filing activity: Jul 23, 1992 → Oct 29, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5313398A | Method and apparatus for simulating a microelectronic circuit | Physics | 75 | Expired |
| US5896300A | Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets | Physics | 57 | Expired |
| US6286126A | Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein | Physics | 39 | Expired |
| US8572523B2 | Lithography aware leakage analysis | Physics | 17 | Active |
| US7434188B1 | Lithographically optimized placement tool | Physics | 2 | Expired |
| US8473876B2 | Lithography aware timing analysis | Physics | 1 | Active |
| US9576098B2 | Lithography aware leakage analysis | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.