Method for design optimization using logical and physical information

US6286128A · kind A · utility

Assignee

• Monterey Design Systems, Inc. · US

Inventors

• Lawrence Pileggi · Pittsburgh, US
• Majid Sarrafzadeh · Villa Park, US
• Sharad Malik · Princeton, US
• Abhijeet Chakraborty · Sunnyvale, US
• Archie Li · Mountain View, US
• Robert E. Shortt · Sunnyvale, US
• Christopher Dunn · Ottawa, CA
• David Gluss · Woodside, US
• Dennis Yamamoto · Los Altos, US
• Dinesh D. Gaitonde · Fremont, US
• Douglas B. Boyle · Palo Alto, US
• Emre Tuncer · Santa Cruz, US
• Eric McCaughrin · Oakland, US
• Feroze P. Taraporevala · Los Altos, US
• Gary K. Yeap · Fremont, US
• James S. Koford · San Jose, US
• Joseph T. Rahmeh · Austin, US
• Lilly Shieh · Union City, US
• Salil Ravindra Raje · Saratoga, US
• Sam Jung Kim · San Jose, US
• Satamurthy Pullela · Cupertino, US
• Yau-Tsun S. Li · Cupertino, US
• Tong Gao · Singapore, SG

Key dates

• Filing date: Jun 12, 1998
• Grant date: Sep 4, 2001
• Expiry date: Jun 12, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/06
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.