Double polysilicon process for providing single chip high performance logic and compact embedded memory structure

US6287913A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Paul D. Agnello · Wappingers Falls, US
• Bomy Chen · Cupertino, US
• Scott W. Crowder · Pleasantville, US
• Ramachandra Divakaruni · Ossining, US
• Subramanian S. Iyer · Yorktown Heights, US
• Dennis Sinitsky · Baoshan, TW

Key dates

• Filing date: Oct 26, 1999
• Grant date: Sep 11, 2001
• Expiry date: Oct 26, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/05

Abstract

A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.