Self aligned channel implant, elevated S/D process by gate electrode damascene
US6287926A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Feb 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.