System and method for residue entrapment utilizing a polish and sacrificial fill for semiconductor fabrication
US6287972A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chemical Mechanical Processing (CMP) is widely used for manufacturing semiconductors. CMP is very effective for planarizing geometry that are not widely isolated. One limiting aspect of CMP is that the deposition of the layer being planarized generally has an effective distance over which gaps can be filled. These gaps can fill with a residue that adversely effects the resultant semiconductor. A technique that inhibits the accumulation of residue deposits a sacrificial layer of material after deposition of a planarizing layer, but before CMP. This layer is selected so that it fills the gaps from the manufacturing process, but has little abrasive or solvent resistance. CMP is performed after the sacrificial layer is performed. However, since the gaps are filled, residues cannot collect. Then, after the CMP is performed, the sacrificial layer is removed by applying a solvent to the sacrificial layer. The choice of material for the sacrificial layer is also important. The sacrificial material must fill the gaps yet be very soluble for removal after the CMP processing is performed. A sacrificial layer having a low viscosity novalac polymer has excellent characteristics for a sacrificia…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.