Semiconductor memory device capable of generating offset voltage independent of bit line voltage
US6288950A · kind A · utility
21Cited by
3References
21Claims
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Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Sep 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells, each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit lines, a plurality of offset circuits, is provided, for applying an offset voltage independent of voltages at the bit lines, to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.