Device and method for generating clock signals from a single reference frequency signal and for synchronizing data signals with a generated clock
US6289067A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S). When in a secondary power savings mode, the pulse swallower produces an output signal having a frequency of chiprate which is used to maintain CDMA network time, permitting th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.