Circuit and method for initiating exception routines using implicit exception checking
US6289445A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jul 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method is provided which allows a microprocessor to implement speculative load instructions with implicit exception checking. In one embodiment of the method, exception information is generated in response to a memory access exception caused by a speculative load instruction for loading one of a plurality of first registers with data from memory. The exception information, once generated, is stored within one of a plurality of second registers. Each of the second registers corresponds to at least one of the plurality of first registers and is configured to store exception information. Thereafter, an instruction for operating on data stored in a first register is received and decoded by the microprocessor. In response, a second register corresponding to the first register is accessed. If this second register contains exception information, then the microprocessor initiates the exception routine. On the other hand, if the second register does not contain exception information, then the instruction for operating on data contained in the first register is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.