Process for underfilling chip-under-chip semiconductor modules
US6291267A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for underfilling a chip-under-chip module. The module comprises a first larger chip, a second smaller chip attached to the underside of the first chip, a substrate having a top surface to which the first chip is mounted, a cavity into which the second chip fits when the first chip is mounted on the top surface, and an access channel connecting the cavity to the top surface. Underfill is disposed under the first chip between the first chip and the substrate, between the first and second chips, within the cavity, and within the access channel. The process for underfilling such a module comprises the steps of forming the substrate having the cavity and access channel in the substrate, connecting the first chip to the substrate, and dispensing underfill through the access channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.