Structure and process for making substrate packages for high frequency application
US6291272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.