Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon
US6291294A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a bottom storage node of a stack capacitor on a substrate is disclosed. The method comprises the steps of: (1) forming a first dielectric layer onto said substrate; (2) forming a nitride layer onto said first dielectric layer; (3) patterning and etching said first dielectric layer and said nitride layer until said substrate is reached, to form a contact opening; (4) forming a first conducting layer into said contact opening and atop said nitride layer; (5) removing a portion of said first conducting layer atop said first dielectric layer to form a plug in said contact opening; (6) forming a second dielectric layer atop said nitride layer and said plug; (7) patterning and etching said second dielectric layer to form a trench above said plug; (8) forming an amorphous polysilicon layer into said trench and atop said second dielectric layer; (9) removing a portion of said amorphous polysilicon layer atop said second dielectric layer; (10) removing remaining portion of said second dielectric layer; and (11) forming an HSG polysilicon layer atop said amorphous polysilicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.