Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer
US6291367A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jun 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of depositing an interlevel dielectric material on a semiconductor wafer at a selected thickness such that the best global planarity of the dielectric layer is achieved. A model for the deposition of a silicon dioxide layer is developed based upon the physics of deposition and sputtering and based upon the minimum geometry of features in the semiconductor device. First the geometric parameters of the metal features are determined. Then, based upon the most aggressive aspect ratio between metal lines, the deposition rate to sputter rate ratio is calculated. The film thickness for optimum global planarity is determined based on the calculated ratio. The dielectric material is then deposited on the metal features using HDP-CVD techniques in a manner using the calculated ratio to stop deposition at the determined film thickness such that the optimum thickness for global planarity is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.