Reduction of process antenna effects in integrated circuits
US6292927A · kind A · utility
17Cited by
17References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach for reducing antenna effects in integrated circuits involves evaluating an integrated circuit design to identify one or more problem interconnects that satisfy certain antenna effect criteria. The problem interconnects are selectively connected to one or more discharge paths and the integrated circuit design is updated to reflect the connections to the one or more discharge paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.