Exposed die leadless plastic chip carrier
US6294100A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Dec 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A leadless integrated circuit package, comprising an exposed semiconductor die and contact pads embedded in an over mold, and wires interconnecting the semiconductor die and contact pads. The leadless integrated circuit package is fabricated by etching a leadframe strip to define a plurality of contact pads; attaching an adhesive film to a bottom surface of the leadframe strip; mounting a semiconductor die to the adhesive film intermediate respective pairs of the contact pads; wire bonding the semiconductor die to the respective pairs of contact pads; encapsulating a top surface of the leadframe strip in a molding material; removing the adhesive film from the bottom surface of the leadframe strip for exposing the contact pads and the semiconductor die; solder plating the exposed bottom surface, and singulating the leadless integrated circuit package from the leadframe strip, whereby the adhesive film holds the semiconductor die in place prior to the encapsulating step, and prevents the molding material from contacting the exposed contact pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.