Implantation mask for producing a memory cell configuration
US6294294A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The memory cell configuration is formed with hybrid memory cells. Individual bit line pairs are isolated from one another by a respective bit line from an adjacent bit line pair, so that the memory cells are arranged relative to one another with 1/4 division. This means that intrinsically cohesive implantation mask parts without connection or corner regions can be used, which avoids implantation problems and still permits production of transistors with a different threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.