Method for controlling thermal interface gap distance
US6294408A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for electronic chip assembly maintains a thin gap spacing between the chip and the lid or heat sink and provides for the electronic chip to operate at a relatively cool temperature. The thermal performance is enhanced by a thermal interface material provided in the thin gap and maintained at a minimal thickness as a result of the structure and assembly process. A thin thermal interface material layer may be achieved with a compression step to compress the thermal interface material before the sealant is cured. In addition, a vent hole is provided in the assembly to prevent pressure build-up inside the module during sealant cure. As the sealant is cured, the gap spacing is maintained, further compression of the thermal interface material is not required, and seal defects are prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.