Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts

US6294416A · kind A · utility

Assignee

• Texas Instruments-Acer Incorporated · TW

Inventor

• Shye-Lin Wu · 東區, TW

Key dates

• Filing date: May 7, 1999
• Grant date: Sep 25, 2001
• Expiry date: May 7, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

The present invention discloses a method of forming CMOS transistors with self-aligned planarization twin-well by using fewer mask counts. After a silicon nitride layer is formed over a first pad oxide layer on a semiconductor substrate, an N-well region is defined by first implanting in the semiconductor substrate. After removing the first photoresist layer, a second ion implantation is performed to define a P-well region. Next, both the silicon nitride layer and the first pad oxide layer are removed. A high temperature long time anneal is done to form a deep twin-well. A plurality of trench isolation regions is formed to define an active area region. A second pad oxide layer is formed on the substrate. A high energy and low dose blanket phosphorous is implanted in a semiconductor substrate for forming a punch-through stopping layer of the PMOSFET device. A low energy and low dose blanket BF.sub.2 implant then adjust both the threshold voltages of the PMOSFET and NMOSFET. Finally, the standard processes can be employed for fabricating the CMOS transistors.