Process of manufacture of a non-volatile memory with electric continuity of the common source lines
US6294431A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Apr 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines. In said step for the definition of the source lines, a process step comprises selectively introducing dopant to form a layer of buried silicon with high concentration of dopant, said layer of buried silicon being formed to such a depth to coincide with the regions of silicon of the underlying field oxide zones, and the introduction of dopant in said active regions of the source lines to superficially contact said layer of buried silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.