Method of manufacturing crown-shaped DRAM capacitor
US6294437A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 16, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Nov 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
Abstract
A method of manufacturing a crown-shaped DRAM capacitor. A silicon oxide layer and a silicon nitride layer are sequentially formed over a substrate. A conductive plug passing through the silicon oxide layer and the silicon nitride layer is formed. A first and a second dielectric layer are sequentially formed over the silicon nitride layer and the conductive plug. A first opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug is formed in the second and the first dielectric layer. A doped amorphous silicon layer conformal to the substrate profile is formed. The doped amorphous silicon layer above the second dielectric layer is removed. The second dielectric layer is next removed, and then hemispherical silicon grains (HSGs) are grown over the exposed surface of the doped amorphous silicon layer. The first dielectric layer is removed, and finally a third dielectric layer and a conductive layer are sequentially formed over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.