Method of dividing a wafer and method of manufacturing a semiconductor device
US6294439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Feb 7, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Grooves are formed in a surface of a wafer, on which semiconductor elements are formed, along dicing lines or chip parting lines on the wafer. The grooves are deeper than the thickness of a finished chip, and each of them has a curved bottom surface. A holding sheet is attached on the surface of the wafer on which the semiconductor elements are formed. Subsequently, the rear surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. Even after the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip. The lapping and polishing amount required to attain the thickness of the finished chip after the lapped face of the wafer reaches the bottom surface of the groove, and a depth of a region of the curved bottom surface of the groove define a ratio of not less than 0.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.