Low cost high density thin film processing
US6294477A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method is provided for high-density thin film interconnect processing. A thin layer of epoxy is deposited over a substrate surface, a via pattern is created in the epoxy layer, the surface of the epoxy is subjected to a process of swell and etch. A metal plating base is formed on the surface of the dielectric using electroless seeding for the metal deposition. A layer of photoresist is deposited over the plating base and is patterned and etched to create the pattern of the interconnect lines. Semi-additive plating of the interconnect pattern is performed to the plating base. The photoresist is removed. The plating base is removed from between the pattern of the interconnect lines using micro etching thereby creating the interconnect lines. A layer of dielectric is deposited over the surface of the created layer of interconnect lines. A via pattern is created in the dielectric layer. The process may be repeated more than once. Electrical contacts are made to the top metal pads through the top vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.