Semiconductor memory device having silicon-on-insulator (SOI) structure and method for fabricating thereof
US6294806A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | May 26, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/928
Abstract
A SOI semiconductor device including a substrate, a first gate electrode formed on a first surface of the substrate between a source/drain region, a first insulating layer formed on the first gate electrode and the first surface of the substrate, a capacitor formed on the first insulating layer, electrically connected to the source/drain region, a second insulating layer formed on the capacitor and the first insulating layer, a third insulating layer formed on a second surface of the substrate, a body contact conductor line formed on and through the third insulating layer in alignment with the first gate electrode, electrically connected to the substrate aligned with the first gate electrode between the source/drain region, a fourth insulating layer formed on the body contact conductor line and the third insulating layer, and a bit line formed on the fourth insulating layer, electrically connected to the source/drain region of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.