Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof
US6294835A · kind A · utility
14Cited by
23References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Aug 2, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.