Programmable logic device
US6294925A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Nov 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/163
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits. This invention may be used to delay output signals which are not time-critical, allowing fast switching of the limited number of time-critical macrocell output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.