Memory device having enhanced programming and/or erase characteristics
US6295226A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 17, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Feb 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.