Inventor · Pleasanton, CA, US

Hsu Kai Yang

33Patents
10h-index
14Co-inventors
72Inventor score

Filing activity: Dec 21, 1998 → Feb 27, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6392427B1 Testing electronic devices Electricity 71 Expired
US7852662B2 Spin-torque MRAM: spin-RAM, array Physics 54 Active
US7613868B2 Method and system for optimizing the number of word line segments in a segmented MRAM array Physics 26 Expired
US6295226A Memory device having enhanced programming and/or erase characteristics Electricity 26 Expired
US7184302B2 Highly efficient segmented word line MRAM array Physics 25 Expired
US7782661B2 Boosted gate voltage programming for spin-torque MRAM array Emerging Cross-Sectional Technologies 18 Active
US7499314B2 Reference cell scheme for MRAM Physics 15 Active
US6977838B1 Method and system for providing a programmable current source for a magnetic memory Physics 13 Expired
US7480172B2 Programming scheme for segmented word line MRAM array Physics 11 Active
US9170879B2 Method and apparatus for scrubbing accumulated data errors from a memory system Physics 10 Active
US7321507B2 Reference cell scheme for MRAM Physics 10 Active
US7085183B2 Adaptive algorithm for MRAM manufacturing Physics 8 Expired
US7362644B2 Configurable MRAM and method of configuration Physics 8 Expired
US8274819B2 Read disturb free SMT MRAM reference cell circuit Physics 6 Active
US8775865B2 Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bits Physics 4 Active
US7977111B2 Devices using addressable magnetic tunnel junction array to detect magnetic particles Emerging Cross-Sectional Technologies 4 Active
US7224628B2 Adaptive algorithm for MRAM manufacturing Physics 4 Active
US8018758B2 Gate drive voltage boost schemes for memory array Physics 3 Active
US7609543B2 Method and implementation of stress test for MRAM Physics 2 Active
US7369430B2 Adaptive algorithm for MRAM manufacturing Physics 2 Active
US8654577B2 Shared bit line SMT MRAM array with shunting transistors between bit lines Physics 2 Active
US7321519B2 Adaptive algorithm for MRAM manufacturing Physics 1 Active
US8248841B2 Boosted gate voltage programming for spin-torque MRAM array Emerging Cross-Sectional Technologies 1 Active
US8437181B2 Shared bit line SMT MRAM array with shunting transistors between the bit lines Physics 1 Active
US7957183B2 Single bit line SMT MRAM array architecture and the programming method Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.