Point-to-point interrupt messaging within a multiprocessing computer system
US6295573A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt messaging scheme to manage interrupts within a multiprocessing computer system without a dedicated interrupt bus. An interconnect structure using a plurality of high-speed dual-unidirectional links to interconnect processing nodes, I/O devices or I/O bridges in the multiprocessing system is implemented. Interrupt messages are transferred as discrete binary packets over point-to-point unidirectional links. A suitable routing algorithm may be employed to route various interrupt packets within the system. Simultaneous transmission of interrupt messages from two or more processing nodes and I/O bridges may be possible without any need for bus arbitration. Interrupt packets carry routing and destination information to identify source and destination processing nodes for interrupt delivery. A lowest priority interrupt packet from an I/O bridge is converted into a coherent form by the host processing node coupled to the I/O bridge. The host node then broadcasts the coherent interrupt packet to all other processing nodes in the system regardless of whether a processing node is identified as a target in the interrupt message packet from the I/O bridge. The host node also receiv…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.