Split directory-based cache coherency technique for a multi-processor computer system
US6295598A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0826
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a "coherency tag" to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques. The technique disclosed may be further expanded to incorporate the "bus lock" capability of bus-based systems compatible with the requirements for multi-processor synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.