Semiconductor device capable of reducing cost of analysis for finding replacement address in memory array
US6297997A · kind A · utility
27Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.