Method and apparatus for programmable control signal generation for a semiconductor device
US6297998A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing of semiconductor memory devices. In one embodiment, a test mode of operation is defined for a memory device. In a normal mode of operation, a row line than addressed memory cell is asserted in response to applied external signals corresponding to the beginning of a write-back phase of a read-modify-write cycle. The row line is deasserted on response to applied external signals corresponding to the end of the write-back phase. In the test mode of operation, the row line is asserted in response to the appropriate applied external signals, but deassertion in response to the appropriate applied external signals is suppressed. Instead, deassertion of the row line is forced only upon expiration of a programmable, predetermined time interval following initiation of the write-back phase. The programmable delay can be established by means of an R-C time constant delay circuit. Programmability may be achieved in various ways, including through the provision of metal options selected during the fabrication process, or, alternatively through the provision of laser-actuable fuses or voltage-actuable antifuses. The programmable forced write-back time facilitate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.