Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

US6300649A · kind A · utility

Assignee

• The Regents of the University of California · US

Inventors

• Chenming Hu · Alamo, US
• Mansun Chan · Hong Kong, CN
• Hsing-Jen Wann · Albany, US
• Ping Keung Ko · Hercules, US

Key dates

• Filing date: Aug 4, 2000
• Grant date: Oct 9, 2001
• Expiry date: Aug 4, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD…