Backside bus vias
US6300670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Jul 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01019
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.