Method and circuit for testing memory cells in a multilevel memory device
US6301157A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells. The method includes reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.