Method and apparatus for dynamic partitionable saturating adder/subtractor
US6301600A · kind A · utility
36Cited by
13References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Nov 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3872
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.