Shared memory bus arbitration system to improve access speed when accessing the same address set
US6301642A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Sep 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus arbitration system is described which includes an arbitrator for controlling accesses to a memory bus by a plurality of memory users in response to requests made by those memory users. Each memory user reads the address if a current access to memory and generates a same-address-set signal when the address of the last access by that memory user lies in the same set as the address of the current access. The arbitrator holds for each memory user a predetermined number of accesses which are permitted by that memory user during an access span, and, responsive to a request, grants up to that predetermined number of accesses provided that the same-address-set signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.