Method for integrating anti-reflection layer and salicide block
US6303406A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises following steps: provide a substrate that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forms a composite layer on the substrate, herein the composite layer at least also covers both sensor area and transistor area, and the composite layer increases refractive index of light that propagate from the doped region into the composite layer; performs an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performs a salicide process to let top of the gate, the source and the drain are covered by a silicate. One main characteristic of the invention is that the composite layer can be used as an anti-reflection layer of the sensor area and a salicide block of the transistor region. The composite layer is made of several basic layers and refractive index of any basic layer is different to refrac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.