Fabrication method for a two-bit flash memory cell
US6303439A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.